In CMOS technology, electrostatic discharge (ESD) protection circuits are traditionally located at each signal line pad of each integrated circuit chip needing protection. ESD circuits are also sometimes located between the power supply rails of the integrated circuit chip.
Several problems arise from integrating ESD protection circuits at each signal line pad and between power supply rails. First, ESD protection circuits for chips having a large number of signal lines consume about 5 to 8% of chip area. Therefore, present ESD protection practice adds substantially to the cost of each chip. Second, as the size of devices and wiring on integrated circuit chips scales to smaller and smaller dimensions, the integrated circuit chips become more sensitive to ESD: thinner oxides, shallower junctions, narrower wiring, shorter and narrower channels and the drive to reduce parasitic leakages all tend to increase the ESD sensitivity of a chip and drive up the size and complexity of ESD protection circuits. Third, ESD protection devices built in technologies having shallow trench isolation (STI) structures for isolating adjacent active components from one another have higher resistance, and therefore do not work as well as ESD protection devices built in traditional thermally grown isolation technologies (LOCOS). To compensate for this higher resistance the ESD circuits must be made larger, again driving up manufacturing costs. Fourth, ESD protection devices formed on silicon-on-insulator (SOI) chips have been found to provide less ESD protection than ESD devices formed in bulk silicon, significantly increasing the size of ESD protection devices needed on chips having SOI to achieve ESD performance comparable to that available in traditional bulk silicon. And fifth, with each generation of chip fabrication technology, a significant effort is undertaken to reinvent and redesign ESD protection circuits to accommodate the needs of the new technology, adding to its cost and increasing the time needed to bring the new technology to market.
Potential alternatives, such as providing a portion of an SOI chip with bulk devices, add further to cost and process complexity. Further difficulties, such as crystalline defects may also thereby be introduced.
In addition to ESD circuits, other buffer circuits that are integrated at each signal line pad, such as drivers, receivers, and decoupling capacitors, use a significant amount of chip area. Particular difficulties arise in a mixed voltage environment, in which an integrated circuit chip receives or drives signal at a voltage higher than that used to operate the chip. The higher voltage puts chip yield and reliability at risk because of such well known mechanisms as hot electron degradation, dielectric breakdown, latch up, and MOSFET snapback. Circuit designers have addressed these concerns by incorporating more complex drivers and receivers into the chip, but these measures have driven up the area consumed and lowered the operational performance of the chip. Similarly, the possibility of defects in the dielectrics of large decoupling capacitors connected between power rails of high speed CMOS logic chips provides yield and reliability concerns in addition to area concerns.
A better solution is needed that provides future generations of chips with a high level of ESD protection, capable of operating in a mixed voltage environment, and capable of providing a large amount of decoupling capacitance without consuming a significant part of chip area or degrading chip yield or reliability, and this solution is provided by the following invention.